1) Field of the Invention
The present invention relates to a processor and a pipeline reconfiguration control method in reconfigurable hardware.
2) Description of the Related Art
Recently, there are dynamic reconfigurable techniques for dynamically reconfiguring hardware to suit applications, by using reconfigurable hardware to allow applications to be flexibly handled with while actually executing processing. One example of reconfigurable hardware is an arithmetic and logic unit (ALU) module, which is a circuit that performs processing such as four-arithmetic operations, logic operations, and the like. Performance can be increased by connecting a plurality of ALU modules using a reconfigurable network, and performing pipeline processing that achieves simultaneous parallel operation processing by the ALU modules.
In particular, the number of execution cycles can be effectively reduced by using pipeline processing when executing loop commands. When executing loop commands by pipeline processing, an apparatus has been disclosed that optimizes the arrangement of the loop initial command, and reduces overheads at loop start, by using a loop control apparatus that includes a loop address start register, a loop address end register, a comparator, and a loop counter (Japanese Patent Application Laid-open No. H9-237186 Publication).
However, when pipeline processing has been executed, it is important to determine an opportunity for switching the arrangement of the reconfigurable hardware section (hereinafter, “configuration”), which is, to determine the time when one series of processes has ended, since, when reconfiguration is performed after the series of processes ends, the switching time becomes an overhead of the overall processing and results in performance deterioration.